 |
|
|
To Download STMICROELECTRONICS-M24512-WDW6TPK Datasheet File |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
|
To Download STMICROELECTRONICS-M24512-WDW6TPK Datasheet File |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| june 2010 doc id 16459 rev 19 1/1 1 m24512-r m24512-w m24512-dr 512 kbit serial i2c bus eeprom with three chip enable lines features m24512-r/m2451 2-w: 512 kbit eeprom addressed through the i 2 c bus m24512-dr: 512 kbit eeprom addressed through the i 2 c bus, with additional identification page supports the i 2 c bus modes: ? 1 mhz fast-mode plus ? 400 khz fast mode ? 100 khz standard mode supply voltage ranges: ? 1.8 v to 5.5 v ? 2.5 v to 5.5 v write control input byte and page write (page = 128 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection more than 1 000 000 write cycles more than 40-year data retention packages ?ecopack2 ? (rohs compliant and halogen free) so8 (mw) 208 mils width tssop8 (dw) so8 (mn) 150 mils width ufdfpn8 (mb) 2 3 mm (mlp) www.st.com
contents m24512-r, m24512-w, m24512-dr 2/3 doc id 16459 rev 19 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 addressing the identification page (m24512-dr only) . . . . . . . . . . . . . . . 14 3.7 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 page write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 identification page write (m24512-dr only) . . . . . . . . . . . . . . . . . . . . . . 17 3.11 lock identification page (m24512-dr only) . . . . . . . . . . . . . . . . . . . . . . . 17 3.12 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 3.13 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 19 3.14 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 random address read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 current address read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.17 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 m24512-r, m24512-w, m24512-dr contents doc id 16459 rev 19 3/3 3.18 read identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.19 read identification page status (locked/unlo cked) . . . . . . . . . . . . . . . . . . 22 3.20 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 list of tables m24512-r, m24512-w, m24512-dr 4/4 doc id 16459 rev 19 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code (for memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. device select code to access the identification page (m24512-dr only) . . . . . . . . . . . . . . 11 table 4. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. operating conditions (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. operating conditions (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. dc characteristics (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. dc characteristics (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. so8w ? 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 30 table 17. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 31 table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32 table 19. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21. available m24512-w and m24512-r products (package, voltage range, temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 22. available m24512-dr products (package, voltage range, temperature grade) . . . . . . . . . 35 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 m24512-r, m24512-w, m24512-dr list of figures doc id 16459 rev 19 5/5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. so, ufdfpn and tssop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 10. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. ac test measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 12. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. so8w ? 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 30 figure 14. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31 figure 15. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 description m24512-r, m24512-w, m24512-dr 6/39 doc id 16459 rev 19 1 description the m24512-x devices are i 2 c-compatible electrically er asable programmable memories (eeprom). they are organized as 64 kb 8 bits. the m24512-x can decode the type identifi er code (1010) in accordance with the i 2 c bus definition. the m24512-dr also decodes the type identifier code (1011) when accessing the identification page. the m24512-dr offers an additional identification page (128 bytes) which can be written and (later) permanently locked in read only mode. this identification page can be used for example in the assembly line, to store some application identification parameters. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. figure 1. logic diagram table 1. signal names signal name function direction e0, e1, e2 chip enable inputs sda serial data i/o scl serial clock input wc write control input v cc supply voltage v ss ground ! ) g 3 $ ! 6 # # - x x x 7 # 3 # , 6 3 3 % % m24512-r, m24512-w, m24512-dr description doc id 16459 rev 19 7/39 figure 2. so, ufdfpn and tssop connections 1. see package mechanical data section for package dimensions, and how to identify pin-1. 1 ai04035e 2 3 4 8 7 6 5 sda v ss scl wc e1 e0 v cc e2 signal description m24512-r, m24512-w, m24512-dr 8/39 doc id 16459 rev 19 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 5 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bidirectional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 5 indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code. when not connected (left floating), these inputs are read as low (0,0,0). figure 3. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. when unconnected, the signal is internally read as v il , and write operations are allowed. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i m24512-r, m24512-w, m24512-dr signal description doc id 16459 rev 19 9/39 2.5 v ss ground v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 8 , ta bl e 9 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions v cc has to rise continuously from 0 v up to v cc (min) (see ta bl e 8 , ta bl e 9 ), and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up, the device does not respond to any instruction until v cc reaches an internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage defined in ta b l e 8 , ta b l e 9 . when v cc passes over the por threshold, the device is reset and enters the standby power mode. however, the device must not be accessed until v cc reaches a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range. in a similar way, during power-down (continuous decrease in v cc ), as soon as v cc drops below the power on reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (where v cc decreases continuously), the device must be in the standby power mode (mode reached after decoding a st op condition, assuming that there is no internal write cycle in progress). signal description m24512-r, m24512-w, m24512-dr 10/39 doc id 16459 rev 19 figure 4. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) figure 5. i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) 1 10 100 10 100 1000 b us line c a p a citor (pf) b us line p u ll- u p re s i s tor (k ) when t low = 1. 3 s (min v a l u e for f c = 400 khz), the r bus c bus time con s t a nt m us t b e b elow the 400 n s time con s t a nt line repre s ented on the left. i2c bus m as ter m24xxx r bus v cc c bus s cl s da a i14796 b r bus c bus = 400 n s here r bus c bus = 120 n s 4 k 3 0 pf 1 10 100 10 100 b us line c a p a citor (pf) b us line p u ll- u p re s i s tor (k ) a i14795d i2c bus m as ter m24xxx r bus v cc c bus s cl s da r bus c bus = 270 n s when t low = 700 n s (m a x po ss i b le v a l u e for f c = 1 mhz), the r bus c bus time con s t a nt m us t b e b elow the 270 n s time con s t a nt line repre s ented on the left. when t low = 400 n s (min v a l u e for f c = 1 mhz), the r bus c bus time con s t a nt m us t b e b elow the 100 n s time con s t a nt line repre s ented on the left. here, r bus c bus = 150 n s r bus c bus = 100 n s 5 3 0 m24512-r, m24512-w, m24512-dr signal description doc id 16459 rev 19 11/39 figure 6. i 2 c bus protocol table 2. device select code (for memory array) device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1010e2e1e0rw table 3. device select code to access the identification page (m24512-dr only) device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1011e2e1e0rw scl sda scl sda sda start condition sda input sda change ai00792c stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition signal description m24512-r, m24512-w, m24512-dr 12/39 doc id 16459 rev 19 table 4. most significant address byte b15 b14 b13 b12 b11 b10 b9 b8 table 5. least significant address byte b7 b6 b5 b4 b3 b2 b1 b0 m24512-r, m24512-w, m24512-dr device operation doc id 16459 rev 19 13/39 3 device operation the device supports the i 2 c protocol. this is summarized in figure 6 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the device is always slave in all communications. 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer instruction. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition . 3.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is fo llowed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 3.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 3.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. device operation m24512-r, m24512-w, m24512-dr 14/39 doc id 16459 rev 19 3.5 addressing the memory array to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. 3.6 addressing the identifi cation page (m24512-dr only) the m24512-dr features an additional memory page, referred to as identification page. read and write operations can be performed on this page, except if a lock instruction has been issued to permanently write protect it. the m24512-dr identification page is addressed in the same way as the memory array, except that the 4-bit device type identifier of the device select code is 1011b (see ta b l e 3 ). table 6. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x re-start, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 128 start, device select, rw = 0 m24512-r, m24512-w, m24512-dr device operation doc id 16459 rev 19 15/39 figure 7. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120d page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack device operation m24512-r, m24512-w, m24512-dr 16/39 doc id 16459 rev 19 3.7 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 8 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if write control (wc ) is driven high. any write instruction with write control (wc ) driven high (during a period of time from the start condition until the end of the two address byte s) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 7 . each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte ( ta b l e 4 ) is sent first, followed by the least significant byte ( ta bl e 5 ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. 3.8 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 8 . 3.9 page write (memory array) the page write mode allows up to or 128 bytes to be written in a single write cycle, provided that they are all lo cated in the same ?row? in the memory: that is, the most significant memory address bits (b15-b7) are the same . if more bytes are sent than will fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to or 128 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. m24512-r, m24512-w, m24512-dr device operation doc id 16459 rev 19 17/39 3.10 identification page write (m24512-dr only) the identification page (128 bytes) is written by issuing an identification page write instruction. this instruction uses the same protocol and format as the page write in memory array, except for the following differences: device type identifier = 1011b msb address bits a15/a7 are don't care except for address bit a10 which must be ?0?. lsb address bits a6/a0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the identification page write instruction are not acknowledged (noack). 3.11 lock identification page (m24512-dr only) the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is similar to byte write (into memory array) with the following specific conditions: device type identifier = 1011b address bit a10 must be ?1?; all other address bits are don't care the data byte must be equal to the binary value xxxx xx1x, where x is don't care. if the identification page is locked, the data bytes transferred during the id write instruction are not acknowledged (noack). 3.12 ecc (error correction code) and write cycling the m24512-x devices offer an ecc (error correction code) logic which compares each 4- byte word with its six associated ecc eeprom bits . as a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ecc detects it and replaces it by the correct value. the r ead reliability is ther efore much improved by the use of this feature. note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ecc bits), that is, the addressed byte is cycled together with the other three bytes making up the word. it is therefore recommended to write by word (4 bytes) in order to benefit from the larger amount of write cycles. the m24512-x devices are qualified at 1 million (1 0 00 000) write cycles, using a cycling routine that writes to the device by multiples of 4-bytes. device operation m24512-r, m24512-w, m24512-dr 18/39 doc id 16459 rev 19 figure 8. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106d page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack m24512-r, m24512-w, m24512-dr device operation doc id 16459 rev 19 19/39 figure 9. write cycle polling flowchart using ack 3.13 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in ta b l e 1 4 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 9 , is: initial condition: a writ e cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847d next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation device operation m24512-r, m24512-w, m24512-dr 20/39 doc id 16459 rev 19 3.14 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device?s internal address counter is incremented by one, to point to the next byte address. figure 10. read mode sequences 3.15 random address read (in memory array) a dummy write is first performed to load the address into this address counter (as shown in figure 10 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. start dev sel * byte addr byte addr start dev sel data out 1 ai01105d data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack m24512-r, m24512-w, m24512-dr device operation doc id 16459 rev 19 21/39 3.16 current address re ad (in memory array) for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 10 , without acknowledging the byte. 3.17 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 10 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 3.18 read identification page the identification page can be read by issuing an id read instruction. this instruction uses the same protocol and format as the random address read (from memory array) with the device type identifier defined as 1011b. the msb address bits a17 to a7 are ?don?t care?. the lsb address bits a6 to a0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g. when reading the identification page from location 100d, the number of bytes should be less than or equal to 28, as the id page boundary in 128 bytes). if the identification page is locked, the data bytes are read as ffh. device operation m24512-r, m24512-w, m24512-dr 22/39 doc id 16459 rev 19 3.19 read identification page status (locked/unlocked) the locked/unlocked status of the identification page can be checked by issuing a specific truncated instruction consisting of the identification page write instruction (see section 3.10 ) followed by one data byte. the da ta byte will be ac knowledged if the identification page is unlocked, while it will not be acknowledged if the identification page is locked. once the acknowledge bit of this data byte is read, it is recommended to generate a start condition followed by a st op condition, so that: the instruction is truncated and not executed as the start condition resets the device internal logic. the device is set to standby mode by the stop condition. 3.20 acknowledge in read mode for all read instructions, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. m24512-r, m24512-w, m24512-dr initial delivery state doc id 16459 rev 19 23/39 4 initial delivery state the device is delivered with all bits in the memory array set to 1 (each byte contains ffh). 5 maximum rating stressing the device outside the ratings listed in ta bl e 7 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings symbol parameter min. max. unit ambient temperature with power applied ?55 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for smal l body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on the restriction of the use of certain hazardous substances in electr ical and electronic equip ment (rohs) 2002/95/ec. c v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v i ol dc output current (sda = 0) 5 ma v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant wi th jedec std jesd22-a114, c1 = 100 pf, r1 = 1500 , r2 = 500 ) ?3000 3000 v dc and ac parameters m24512-r, m24512-w, m24512-dr 24/39 doc id 16459 rev 19 6 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 11. ac test measurement i/o waveform table 8. operating conditions (voltage range w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 c table 9. operating conditions (voltage range r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 10. ac test measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf scl input rise/fall time, sda input fall time 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels m24512-r, m24512-w, m24512-dr dc and ac parameters doc id 16459 rev 19 25/39 table 11. input parameters symbol parameter (1) 1. sampled only, not 100% tested. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l (2) 2. e2,e1,e0: input impedance when the memory is selected (after a start condition). input impedance (e2, e1, e0, wc ) v in < 0.3v cc 30 k z h (2) input impedance (e2, e1, e0, wc ) v in > 0.7v cc 500 k table 12. dc characteristics (voltage range w) symbol parameter test conditions (see table 8 and table 10 ) min. max. unit i li input leakage current (scl, sda, e0, e1, e2) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 1 (1) 1. the new m24512-w devices (identified by the process letter k) offer i cc =1.5ma. ma v cc = 5.5 v, f c = 400 khz (rise/fall time < 50 ns) 2ma v cc = 2.5 v, f c = 1 mhz (2) (rise/fall time < 50 ns) 2. only for devices operating at the f c max = 1 mhz (see table 15 ) 2.5 ma v cc = 5.5 v, f c = 1 mhz (2) (rise/fall time < 50 ns) 2.5 ma i cc0 supply current (write) during t w , 2.5 v < v cc < 5.5 v 5 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 2.5 v 4. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). device grade 3 5 a device grade 6 2 v in = v ss or v cc , v cc = 5.5 v 5 a v il input low voltage (scl, sda, wc ) ?0.45 0.3v cc v v ih input high voltage (scl, sda) 0.7v cc 6.5 v input high voltage (w c , e0, e1, e2) 0.7v cc v cc +0.6 v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v 0.4 v dc and ac parameters m24512-r, m24512-w, m24512-dr 26/39 doc id 16459 rev 19 table 13. dc characteristics (voltage range r) symbol parameter test conditions (in addition to those in table 9 and table 10 ) (1) 1. if the application uses the vo ltage range r device within 2.5 dc and ac parameters m24512-r, m24512-w, m24512-dr 28/39 doc id 16459 rev 19 table 15. 1 mhz ac characteristics (1) 1. only new m24512-r and m24512-dr devices identified by the process letter k are qualified at 1 mhz. test conditions specified in table 9 and table 10 symbol alt. parameter min. (2) 2. all values are referred to v il (max) and v ih (min). max. (2) unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 300 - ns t clch t low clock pulse width low 400 - ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz, or less than 120 ns when f c <1mhz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t ql1ql2 (4) 4. characterized only, not tested in production. t f sda (out) fall time 20 (5) 5. with c l = 10 pf. 120 ns t dxcx t su:dat data in setup time 80 - ns t cldx t hd:dat data in hold time 0 - ns t clqx t dh data out hold time 50 (6) 6. the new m24xxx devices (identified by the process letter k) offer t clqx =100 ns (min) and t clqv =100 ns (min) which is an improved value compared to the t clqx =50 ns (min) and t clqv =50 ns (min) offered by the current m24xxx devices (identif ied with the process letter a) -ns t clqv (7)(8) 7. to avoid spurious start and st op conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. 8. t clqv is the time (from the falling edge of scl) required by the sda bus line to reach 0.8v cc , assuming that the r bus c bus time constant is within the values specified in figure 5 . t aa clock low to next data valid (access time) 50 (6) 500 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t w t wr write time - 5 ms t ns (4) pulse width ignored (input filter on scl and sda) -50 (9) 9. the new m24xxx devices (identified with the process letter k) offer t ns = 80 ns (min) which is an improved value compared to the current m24xxx devi ces (identified by the process letter a). ns m24512-r, m24512-w, m24512-dr dc and ac parameters doc id 16459 rev 19 29/39 figure 12. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdl start condition tclch tdxch tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdl start condition write cycle tw ai00795e start condition tchcl txh1xh2 txh1xh2 txl1xl2 txl1xl2 data valid tql1ql2 package mechanical data m24512-r, m24512-w, m24512-dr 30/39 doc id 16459 rev 19 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 13. so8w ? 8-lead plastic small outline, 208 mils body width, package outline 1. drawing is not to scale. table 16. so8w ? 8-lead plastic small outline, 208 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 2.5 0.0984 a1 0 0.25 0 0.0098 a2 1.51 2 0.0594 0.0787 b 0.4 0.35 0.51 0.0157 0.0138 0.0201 c 0.2 0.1 0.35 0.0079 0.0039 0.0138 cp 0.1 0.0039 d 6.05 0.2382 e 5.02 6.22 0.1976 0.2449 e1 7.62 8.89 0.3 0.35 e 1.27 - - 0.05 - - k 0 10 0 10 l 0.5 0.8 0.0197 0.0315 n (number of pins) 8 8 6l_me e n cp b e a2 d c l a1 k e1 a 1 m24512-r, m24512-w, m24512-dr package mechanical data doc id 16459 rev 19 31/39 figure 14. so8n ? 8-lead plastic small outlin e, 150 mils body width, package outline 1. drawing is not to scale. table 17. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.75 0.0689 a1 0.1 0.25 0.0039 0.0098 a2 1.25 0.0492 b 0.28 0.48 0.011 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.1 0.0039 d 4.9 4.8 5 0.1929 0.189 0.1969 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h 0.25 0.5 0.0098 0.0197 k 08 08 l 0.4 1.27 0.0157 0.05 l1 1.04 0.0409 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane package mechanical data m24512-r, m24512-w, m24512-dr 32/39 doc id 16459 rev 19 figure 15. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1 m24512-r, m24512-w, m24512-dr package mechanical data doc id 16459 rev 19 33/39 figure 16. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline 1. drawing is not to scale. 2. the central pad (the area e2 by d2 in the abov e illustration) is pulle d, internally, to v ss . it must not be allowed to be connected to any other voltage or sig nal line on the pcb, for example during the soldering process. 3. the circle in the top view of the package indicates the position of pin 1. table 19. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 0.55 0.45 0.6 0.0217 0.0177 0.0236 a1 0.02 0 0.05 0.0008 0 0.002 b 0.25 0.2 0.3 0.0098 0.0079 0.0118 d 2 1.9 2.1 0.0787 0.0748 0.0827 d2 1.6 1.5 1.7 0.063 0.0591 0.0669 e 3 2.9 3.1 0.1181 0.1142 0.122 e2 0.2 0.1 0.3 0.0079 0.0039 0.0118 e 0.5 - - 0.0197 - - l 0.45 0.4 0.5 0.0177 0.0157 0.0197 l1 0.15 0.0059 l3 0.3 0.0118 ddd (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. 0.08 0.08 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l 3 part numbering m24512-r, m24512-w, m24512-dr 34/39 doc id 16459 rev 19 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 20. ordering information scheme example: m24512? w mw 6 t p /ab device type m24 = i 2 c serial access eeprom device function 512? = 512 kbit (64 kb 8) device family blank: without identification page d: with additional identification page operating voltage w = v cc = 2.5 to 5.5 v r = v cc = 1.8 to 5.5 v package mw = so8 (208 mils width) mn = so8 (150 mils body width) dw = tssop8 mb = ufdfpn8 device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 = automotive: device tested with high reliability certified flow (1) over ?40 to 125 c option blank = standard packing t = tape and reel packing plating technology p or g = ecopack ? (rohs compliant) process (2) /ab = f8l process (for device grade 3) /k = f8h process 1. st strongly recommends the use of the automotive gr ade devices for use in an aut omotive environment. the high reliability certified flow (hrcf) is des cribed in the quality note qnee9801. please ask your nearest st sales office for a copy. 2. used only for device grade 3. m24512-r, m24512-w, m24512-dr part numbering doc id 16459 rev 19 35/39 table 21. available m24512-w and m24512-r products (package, voltage range, temperature grade) package m24512-w 2.5 v to 5.5 v m24512-r 1.8 v to 5.5 v so8n (mn) range 6, range 3 range 6 so8w (mw) range 6 - tssop (dw) range 6 range 6 ufdfpn8 (mb) - range 6 wlcsp (cs) - range 6 table 22. available m24512-dr products (package, voltage range, temperature grade) package m24512-dr 1.8 v to 5.5 v so8n (mn) range 6 tssop (dw) range 6 ufdfpn8 (mb) range 6 revision history m24512-r, m24512-w, m24512-dr 36/39 doc id 16459 rev 19 9 revision history table 23. document revision history date revision changes 29-jan-2001 1.1 lead soldering temperature in the absolute maximum ratings table amended write cycle polling flow chart using ack illustration updated lga8 and so8(wide) packages added references to psdip8 changed to pdip8, and package mechanical data updated 10-apr-2001 1.2 lga8 package mechanical data and illustration updated so16 package removed 16-jul-2001 1.3 lga8 package given the designator ?la? 02-oct-2001 1.4 lga8 package mechanical data updated 13-dec-2001 1.5 document becomes preliminary data test conditions for ili, ilo, zl and zh made more precise vil and vih values unified. tns value changed 12-jun-2001 1.6 document promoted to full datasheet 22-oct-2003 2.0 table of contents, and pb-free opti ons added. minor wording changes in summary description, power-on re set, memory addressing, write operations, read operations. v il (min) improved to ?0.45v. 02-sep-2004 3.0 lga8 package is not for new design. 5v and -s supply ranges, and device grade 5 removed. abso lute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade information clarified. aec-q100-002 compliance. v il specification unified for sda, scl and wc 22-feb-2005 4.0 initial delivery state is ffh (not necessarily the same as erased). lga package removed, tssop8 and so8n packages added (see package mechanical data section and table 20: ordering information scheme ). voltage range r (1.8v to 5.5v) also offered. minor wording changes. z l test conditions modified in table 11: input parameters and note 2 added. i cc and i cc1 values for v cc = 5.5v added to table 12: dc characteristics (voltage range w) . note added to table 12: dc characteristics (voltage range w) . power on reset paragraph specified. t w max value modified in table 14: 400 khz ac characteristics and note 4 added. plating technology changed in table 20: ordering information scheme . resistance and capacitance renamed in figure 5 . m24512-r, m24512-w, m24512-dr revision history doc id 16459 rev 19 37/39 05-may-2006 5 power on reset paragraph replaced by section 2.6: supply voltage (v cc ) . figure 3: device select code added. ecc (error correction code) and write cycling added and specified at 1 million cycles. i cc0 added and i cc1 specified over the whole voltage range in ta b l e 1 2 and ta bl e 1 3 . pdip8 package removed. packages are ecopack? compliant. small text changes. 16-oct-2006 6 m24256-bw and m24256-br part numbers added. section 3.12: ecc (error corre ction code) and write cycling updated. i cc and i cc1 modified in table 13: dc characteristics (voltage range r) . t w modified in table 14: 400 khz ac characteristics . so8narrow package specifications updated (see ta b l e 1 7 and figure 14 ). blank option removed from below plating technology in table 20: ordering information scheme . 02-jul-2007 7 section 2.6: supply voltage (v cc ) modified. section 3.12: ecc (error corre ction code) and write cycling modified. jedec standard and european direct ive references corrected below table 7: absolute maximum ratings . rise/fall time conditions modified for i cc and v ih max modified in table 12: dc characteristics (voltage range w) and table 13: dc characteristics (voltage range r) note 1 removed from table 12: dc characteristics (voltage range w) . so8w package specifications modified in section 7: package mechanical data . table 23: available m24256-br, m24256-bw, m24256-bf products (package, voltage range, temperature grade) and table 26: available m24512-x products (package, voltage range, temperature grade) added. 16-oct-2007 8 section 2.5: v ss ground added. small text changes. v io max changed and note 1 updated to latest standard revision in table 7: absolute maximum ratings . note removed from table 11: input parameters . v ih min and v il max modified in table 13: dc characteristics (voltage range r) . removed t ch1ch2 , t cl1cl2 and t dh1dh2 , and added t xl1xl2 , t dl1dl2 and note 3 in table 14: 400 khz ac characteristics . t xh1xh2 , t xl1xl2 and note 2 added to table 15: 1 mhz ac characteristics . figure 12: ac waveforms modified. package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see section 7: package mechanical data ). table 23. document revision history (continued) date revision changes revision history m24512-r, m24512-w, m24512-dr 38/39 doc id 16459 rev 19 14-dec-2007 9 1 mhz frequency introduced (m24512-hr root part number). section 2.6.3: device reset modified. figure 4: i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) modified, figure 5: i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) added. t ns moved from ta b l e 1 1 to ta b l e 1 4 . i lo test conditions modified in ta b l e 1 2 . table 13: dc characteristics (voltage range r) and table 15: 1 mhz ac characteristics modified. small text changes. 27-mar-2008 10 small text changes. m24256-bhr root part number added. section 2.6.3: device reset on page 9 updated. figure 5: i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) on page 10 updated. caution removed in section 3.12: ecc (error correction code) and write cycling . 22-apr-2008 11 m24512-w and m24256-bw offered in the device grade 3 option (automotive tem perature range): ? table 8: operating conditions (voltage range w) , ? table 12: dc characteristics (voltage range w) , ? /ab process letters added to table 20: ordering information scheme , ? table 23: available m24256-br, m24256-bw, m24256-bf products (package, voltage range, temperature grade) and ? table 26: available m24512-x products (package, voltage range, temperature grade) updated accordingly). small text changes. 22-dec-2008 12 wlcsp package added (see figure 3: wlcsp connections (top view, marking side, with balls on the underside) and section 7: package mechanical data ). 21-jan-2009 13 m24256-bf part number added (v cc = 1.7 v to 5.5 v voltage range added, see ta bl e 1 0 , ta b l e 1 4 and table 23). i cc1 test conditions modified in table 12: dc characteristics (voltage range w) , table 13: dc characteristics (voltage range r) and ta bl e 1 4 : dc characteristics (voltage range f) . 05-jun-2009 14 m24512-dr part number and ident ification page feature added. command replaced by instruction in the whole document. ufdfpn8 added. figure 5 updated. section 2.6.2: power-up conditions and section 2.6.3: device reset updated. t clqx and t clqv updated in ta bl e 1 4 , note 5 and note 8 added. t clqx and t clqv updated in ta b l e 1 5 , note 6 and note 9 added. section 8: part numbering updated. reference to the sure program removed in section 5: maximum rating . previous 1 mhz m24512-hr and m24512-bhr devices replaced by new m24512-r and m24256-br (process letter k). table 23. document revision history (continued) date revision changes m24512-r, m24512-w, m24512-dr revision history doc id 16459 rev 19 39/39 16-jun-2009 15 part numbers updated in cover page header. 20-aug-2009 16 i ol added to table 8: operating conditions (voltage range w) . note 1 and i cc modified in table 12: dc characteristics (voltage range w) ; note 2 and i cc modified in table 13: dc characteristics (voltage range r) ; 13-oct-2009 17 datasheet split to leave only devices with 512 kbit capacity. figure 3: device select code and figure 4: i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) updated. v io max modified in table 7: absolute maximum ratings . v ih modified in table 12: dc characteristics (voltage range w) , ta bl e 1 3 : dc characteristics (voltage range r) and table 14: dc characteristics (voltage range f) . in table14: 400khz ac characteristics and table 15: 1 mhz ac characteristics : ?t dl1dl2 changed to t ql1ql2 ?t chdx changed to t chdl ?t xh1xh2 and t xl1xl2 values removed ? notes modified figure 12: ac waveforms modified. 05-nov-2009 18 section 3.10: identification page write (m24512-dr only) corrected. section 3.18: read identification page clarified. 01-jun-2010 19 clarified cover page. section 1: description inserted paragraph clarifying identification page. section 3.1: start condition clarified. section 3.7: write operations clarified. section 3.10: identification page write (m24512-dr only) clarified. section 3.18: read identification page paragraph updated. table 7: absolute maximum ratings updated. table 10: ac test measurement conditions updated. table 12: dc characteristics (voltage range w) updated. table 13: dc characteristics (voltage range r) updated. table 14: dc characteristics (voltage range f) table deleted. table 23. document revision history (continued) date revision changes m24512-r, m24512-w, m24512-dr 40/40 doc id 16459 rev 19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
Price & Availability of STMICROELECTRONICS-M24512-WDW6TPK
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |